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[原创]Microchip dsPIC33CK256MP508系列数字信号控制器开发方案

Microchip公司的dsPIC33CK256MP508系列数字信号控制器是16位(数据)改进的哈佛架构,具有增强指令集,包括重要支持支持数字信号处理器(DSP).该CPU具有24位指令字,具有可变长度操作码字段.程序计数器(PC)是32位宽,地址多达4Mx24位用户编程存储器空间.指令预取机理有助于维持吞吐量,提供可预测的执行.大多数的指令在单周期有效执行速率中执行,除了改变程序流程的指令,双字传送指令(MOV.D),PSV接入和表格说明.16位 dsPIC33CK 核CPU具有32-256KB带ECC的程序闪存和8-24KB RAM, 代码效率(C和汇编)架构,40位宽累加器,具有双数据提取的单期(MAC/MPY),单周期混合MUL+硬件除法,支持32位乘法,四组中断上下文节省了寄存器,包括了累加器和用于快速中断处理的STATUS, 零开销循环以及内置自测RAM存储器(MBIST).主要用在BLDC, PMSM, ACIM, SR 和步进电动机应用. 此外, DSC还支持开关电源的设计如交流/直流,直流/直流转换器,UPS和PFC,提供高精度数字控制降压,升压,回飞,半桥,全桥, LLC和其他电源电路,以达到最高的能效.本文介绍了dsPIC33CK256MP508系列主要特性,框图和CPU框图,以及50W交叉LLC转换器开发板电特性, 固件结构图,电路图,材料清单和PCB设计图.

The dsPIC33CK256MP508 family CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for Digital Signal Processing (DSP). The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space.

An instruction prefetch mechanism helps maintain throughput and provides predictable execution. Most instructions execute in a single-cycle effective execution rate, with the exception of instructions that change the program flow, the double-word move (MOV.D)

instruction, PSV accesses and the table instructions.

Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

dsPIC33CK256MP508系列主要特性:

Operating Conditions

• 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS

• 3.0V to 3.6V, -40°C to +150°C, DC to 70 MIPS

Core: 16-Bit dsPIC33CK CPU

• 32-256 Kbytes of Program Flash with ECC and 8-24K RAM

• Fast 6-Cycle Divide

• LiveUpdate

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus Hardware Divide

• 32-Bit Multiply Support

• Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling

• Zero Overhead Looping

• RAM Memory Built-In Self-Test (MBIST)

Clock Management

• Internal Oscillator

• Programmable PLLs and Oscillator Clock Sources

• Reference Clock Output

• Fail-Safe Clock Monitor (FSCM)

• Fast Wake-up and Start-up

• Backup Internal Oscillator

Power Management

• Low-Power Management Modes (Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

High-Speed PWM

• Eight PWM Pairs

• Up to 250 ps PWM Resolution

• Dead Time for Rising and Falling Edges

• Dead-Time Compensation

• Clock Chopping for High-Frequency Operation

• PWM Support for:

- DC/DC, AC/DC, inverters, PFC, lighting

- BLDC, PMSM, ACIM, SRM motors

• Fault and Current Limit Inputs

• Flexible Trigger Configuration for ADC Triggering

Timers/Output Compare/Input Capture

• One General Purpose Timer

• Peripheral Trigger Generator (PTG):

- Up to 15 trigger sources to other peripheral modules

- CPU independent state machine-based instruction sequencer

• Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM:

- One MCCP

- Eight SCCPs

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

• Fully Asynchronous Operation, Available in Sleep Modes

Advanced Analog Features

• High-Speed ADC module:

- 12-bit with two dedicated SAR ADC cores and one shared SAR ADC core

- Configurable resolution (up to 12-bit) for each ADC core

- Up to 3.5 Msps conversion rate per channel at 12-bit resolution

- Up to 24 input channels

- Dedicated result buffer for each analog channel

- Flexible and independent ADC trigger sources

- Four digital comparators

- Four oversampling filters for increased resolution

• Up to Three Analog Comparators:

- 15 ns analog comparator

• Up to Three Op Amps

• Three 12-Bit DACs:

- Hardware slope compensation

Communication Interfaces

• Three Protocol UARTs with Automated Protocol Handling Support for:

- LIN 2.2

- DMX

- IrDA®

• 3 Four-Wire SPI/I2S modules

• CAN Flexible Data (FD) module

• Three I2C modules with SMBus Support

• PPS to Allow Function Remap

• Programmable Cyclic Redundancy Check (CRC)

• Two SENT modules

• Parallel Master Port (PMP)

Direct Memory Access (DMA)

• Four DMA Channels

Debugger Development Support

• In-Circuit and In-Application Programming and Debugging

• Three Complex, Five Simple Breakpoints

• IEEE 1149.2 Compatible (JTAG) Boundary Scan

• Trace Buffer and Run-Time Watch

Safety Features

• Clock Monitor System with Backup Oscillator

• DMT (Deadman Timer)

• ECC (Error Correcting Code)

• WDT (Watchdog Timer)

• CodeGuard™ Security

• CRC (Cyclic Redundancy Check)

• Flash OTP by ICSP™ Write Inhibit

• RAM Memory Built-In Self-Test (MBIST)

• Two-Speed Start-up

• Fail-Safe Clock Monitoring (FSCM)

• Backup FRC (BFRC)

• Capless Internal Voltage Regulator

• Virtual Pins for Redundancy and Monitoring

Functional Safety

• Class B Safety Library – IEC 60730

• For ASIL B and Beyond Applications – ISO 26262

• FMEDA Computation Spreadsheet (Evaluation of Random Hardware Failures Metric)

• Functional Safety Manual

• Functional Safety Diagnostics Suite

Qualification Support

• AEC-Q100 REV-H (Grade 1: -40°C to +125°C) Compliant

• AEC-Q100 REV-H (Grade 0: -40°C to +150°C) Compliant

图1. dsPIC33CK256MP508系列框图

图2. dsPIC33CK256MP508系列CPU框图

图3. dsPIC33CK256MP508系列推荐连接图

dsPIC33CK256MP508系列目标应用:

• Power Factor Correction (PFC):

- Interleaved PFC

- Critical Conduction PFC

- Bridgeless PFC

• DC/DC Converters:

- Buck, Boost, Forward, Flyback, Push-Pull

- Half/Full-Bridge

- Phase-Shift Full-Bridge

- Resonant Converters

• DC/AC:

- Half/Full-Bridge Inverter

- Resonant Inverter

• Motor Control

- BLDC

- PMSM

- SR

- ACIM

图4.交叉PFC框图

图5.相移全桥转换器框图

图6.离线UPS框图

50W交叉LLC转换器开发板

50W Interleaved LLC Converter Development Board

This users guide describes how to use the 50W Interleaved LLC Converter Development

Board. The device-specific data sheets contain current information on programming the

specific microcontroller or digital signal controller devices. Other useful document(s) are

listed below. The following Microchip document(s) are recommended as supplemental

reference resources.

The 50W Interleaved LLC Converter Development Board is a generic development board for this topology that supports rapid prototyping and code development based on dsPIC33 devices. The board provides two identical half-bridge stages with LLC tank circuitry at the primary and voltage doubler rectification at the secondary. The board offers well organized building blocks that include an input filter, power stage, AUX supply, mating socket for Microchips newest Digital Power Plug-In Modules (DP PIMs), Human Machine Interface (HMI) and test points.

The electrical characteristics are prepared to allow safe voltage levels of up to 50 VDC in

and up to 12 VDC out. Topology and design are scalable and can be easily turned into real industrial demands targeting 400 VDC or 800 VDC bus operating voltage. A mating

socket for dsPIC33 plug-in modules allows the system to be evaluated with different

controllers. The pinout is compatible for EP, CK and CH dsPIC® DSC DP PIMs.