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首页>解决方案>[原创]NXP VR5510多输出电源管理(PMIC)解决方案

[原创]NXP VR5510多输出电源管理(PMIC)解决方案

NXP公司的VR5510是汽车多输出电源管理集成电路(PMIC),目标应用在网关,车内网络,域控制器,远程信号系统和V2X通信.器件包括多个高效开关模式和线性电压稳压器.它提供输入和输出外接频率同步,以最优化系统EMC性能. VR5510包括增强的安全特性和故障安全的输出.器件满足ASILB和ASILD安全水平,和ISO 26262标准兼容,和AEC-Q100 rev H (Grade1, MSL3)兼容的认证. VR5510最大输入电压为60VDC,VPRE同步降压控制器具有外接MOSFET,可配置输出电压,开关频率,电流能力高达10A.低压集成的同步BUCK1和BUCK2转换器专给MCU核供电,具有SVS/DVS功能,可配置输出电压和电流能力高达3.6A峰值,双向工作可扩展电流到7.2A峰值.低压集成的同步BUCK3转换器,可配置输出电压和电流能力高达3.6A峰值.BOOST转换器集成了低边开关,可配置输出电压和电流能力高达2.25A峰值.3x线性稳压器(LDOx)给MCU IO,DDR和ADC供电,可配置输出电压和电流高达400mA.高压线性稳压器(HVLDO)电流能力在LDO模式为10mA,开关模式为100mA.EMC优化技术包括SMPS频率同步,扩展频谱,转换速率控制和人工频率调谐.本文介绍了VR5510主要特性和优势,内部框图和简化应用框图,时钟管理框图,应用电路图和评估板KITVR5510xA0EVM主要特性,电路图,材料清单和PCB设计图.

 

The VR5510 is an automotive multi-output power management IC that focuseson Gateway, In-Vehicle Networks, Domain controllers, Telematics and V2XCommunications. The device includes multiple high-efficiency switch modes and linearvoltage regulators. It offers external frequency synchronization on inputs and outputs foroptimized system EMC performance.

The VR5510 includes enhanced safety features with fail-safe outputs. The device covers

ASIL B and ASIL D safety integrity levels. It complies with the ISO 26262 standard and is

qualified in accordance with AEC-Q100 rev H (Grade1, MSL3). The VR5510 can be fully

utilized in safety-oriented system partitioning and can also be configured to operate as a

nonsafety QM-version part.

The VR5510 is available in several versions that support a variety of safety applications

and offer numerous choices with respect to the number of output rails, output voltage

settings, operating frequencies, and power-up sequencing.

VR5510主要特性和优势:

•60 VDC maximum input voltage

•VPRE synchronous buck controller with external MOSFETs; Configurable outputvoltage, switching frequency, and current capability up to 10 A

•Low-voltage integrated synchronous BUCK1 and BUCK2 converters dedicated toMCU core supply with SVS/DVS capability; Configurable output voltage and currentcapability up to 3.6 A peak; Dual-phase operation to extend the current capability up to7.2 A peak

•Low-voltage integrated synchronous BUCK3 converter; Configurable output voltageand current capability up to 3.6 A peak

•BOOST converter with integrated low-side switch; Configurable output voltage andinput current capability up to 2.25 A peak

•3x linear voltage regulators (LDOx) for MCU IOs, DDR and ADC supplies; Configurable

output voltage and current capability up to 400 mA

•High-voltage linear regulator (HVLDO) with current capability up to 10 mA in LDO mode

and 100 mA in Switch Mode

•EMC optimization techniques, including SMPS frequency synchronization, spread

spectrum, slew rate control, manual frequency tuning

•Low-power standby mode with very low quiescent current (35 μA with VPRE andHVLDO ON)

•2x input pins for wake-up detection and battery voltage sense

•Device control via I2C interface with CRC (up to 3.4 MHz)

•Dual device operation possible via dedicated synchronization pin

•Scalable portfolio from QM to ASIL B to ASIL D with Independent Monitoring Circuitry,

dedicated interface for MCU monitoring, simple and challenger watchdog function,Power good, Reset and Interrupt, Built-in Self-Test, Fail-safe output

•Configuration by OTP programming; Prototype enablement to support custom setting

during project development in engineering mode

VR5510应用:

•Gateway

•In-Vehicle Networks

•Domain controllers

•Telematics

•V2X Communications

 

图1.VR5510内部框图

 

图2. VR5510简化应用框图

 

图3.VR5510时钟管理框图

 

图4.VR5510应用电路图

评估板KITVR5510xA0EVM

This document is the user guide for the KITVR5510DA0EVM, KITVR5510BA0EVM,

and KITVR5510MA0EVM evaluation boards (referred to throughout this document as

KITVR5510xA0EVM). This document is intended for engineers involved in the evaluation,

design, implementation, and validation of VR5510 Power Management Integrated Circuit

(PMIC) for high performance applications.

The scope of this document is to provide the user with information that covers interfacing

with the hardware, installing the GUI software, using other tools, and configuring theboard for the application environment.

The KITVR5510xA0EVM is the customer evaluation board featuring the VR5510 power management IC. The kit integrates all hardware needed to fully evaluate the featured power management integrated circuit. It integrates a communication bridge based on the FRDM-K82F freedom board to interface with the VR5510 GUI software interface and fully configure and control the VR5510 PMIC.

The KITVR5510xA0EVM is a development platform built around the VR5510 PMIC as

the Device Under Test (DUT). The board allows designers to evaluate various functions

of the DUT. Connectors on the board provide the capability of measuring power-related

functions such as power, efficiency, loop stability, load transients, etc. Jumpers on the

board enable the selection of various capabilities, such as I/O control and switching

regulator feedback. The EVM also allows the VR5510 to be set into Debug Mode to

facilitate the debugging of faults generated by the device.

The KITVR5510xA0EVM includes NXPs FRDM-K82F development platform board.

The FRDM-K82F attaches to the bottom of the board and serves as the communication

interface between the KITVR5510xA0EVM and GUI software on the PC.

评估板KITVR5510xA0EVM主要特性:

•VR5510 debug mode support

•Connectors for measuring:

–Loop stability

–Load transients (BUCK12 or VPRE)

–AMUX/JTAG

–Signal and power

–Efficiency

•Load terminals for VPRE, BUCKs, BOOST, LDOs, and HVLDO regulator output

•Jumper selection for:

–I/O control (RSTB, PGOOD, STANDBY, PWRON2, PSYNC, VDDIO)

–Debug mode entry/exit

–Switching regulators (BUCKx, VPRE) feedback

•Multiple test points

 

图5.评估板KITVR5510xA0EVM外形图:LED,开关和PMIC

 

图6.评估板KITVR5510xA0EVM外形图:连接器

 

图7.评估板KITVR5510xA0EVM外形图:测试点

 

图8.评估板KITVR5510xA0EVM电路图(1)

 

图9.评估板KITVR5510xA0EVM电路图(2)

 

图10.评估板KITVR5510xA0EVM电路图(3)

 

图11.评估板KITVR5510xA0EVM PCB布局图:顶层

 

图12.评估板KITVR5510xA0EVM PCB布局图:层2

 

图13.评估板KITVR5510xA0EVM PCB布局图:层3

 

图14.评估板KITVR5510xA0EVM PCB布局图:层4

 

图15.评估板KITVR5510xA0EVM PCB布局图:层5

 

图16.评估板KITVR5510xA0EVM PCB布局图:层6

 

图17.评估板KITVR5510xA0EVM PCB布局图:层7

 

图18.评估板KITVR5510xA0EVM PCB布局图:底层

 

评估板KITVR5510xA0EVM材料清单:

 

 

 

详情请见:

https://www.nxp.com.cn/docs/en/data-sheet/VR5510.pdf

https://www.nxp.com.cn/docs/en/user-guide/UM11587.pdf

以及

https://www.nxp.com.cn/downloads/en/schematics/KITVR5510XA0EVM-SCH.pdf

KITVR5510XA0EVM-SCH.pdf

UM11587.pdf

VR5510.pdf