Lattice公司的iCE40系列超低功耗非易失性FPGA,查找表(LUT)从384到7680,并具有嵌入区块RAM(EBR), 非易失性可配置存储器(NVCM)和锁相环(PLL),采用40nm低功耗工艺,待机功耗低至21uW,非常适合用在低成本量达的消费类电子和系统应用.本文介绍了iCE40系列FPGA主要特性和架构图, iCEblink40-LP1K评估板主要特性,电路图和主要元件清单.

The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer High-Current drivers that are ideal to drive three white LEDs, or one RGB LED. The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices. The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40x1.48mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters. The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a “per-pin” basis. The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

iCE40系列FPGA主要特性:

 Flexible Logic Architecture
• Five devices with 384 to 7,680 LUT4s and  10 to 206 I/Os
 Ultra Low Power Devices
• Advanced 40 nm low power process
• As low as 21 μW standby power
• Programmable low swing differential I/Os
 Embedded and Distributed Memory
• Up to 128 Kbits sysMEM™ Embedded Block RAM
 Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
 High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
• Programmable pull-up mode
 Flexible On-Chip Clocking
• Eight low-skew global clock resources
• Up to two analog PLLs per device
 Flexible Device Configuration
• SRAM is configured through:
 Broad Range of Package Options
• WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options
• Small footprint package options
• Advanced halogen-free packaging

The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Non-volatile Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO).

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large 4 Kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have mul-tiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 includes on-chip, Nonvolatile Configuration Memory (NVCM).

图1. iCE40LP/HX1K器件架构图(顶视)

iCEblink40-LP1K评估板

This guide describes how to begin using the iCEblink40-LP1K Evaluation Kit, an easy-to-use platform for rapidly prototyping designs using the iCE40™ FPGA.

iCEblink40-LP1K评估板主要特性:

• Ultra low-power iCE40LP1K FPGA
• USB programming, debugging, virtual I/O functions, and power supply
• Four user LEDs
• Four capacitive-touch buttons
• 3.3 MHz clock source
• 1Mbit SPI serial configuration PROM
• Supported by Lattice iCEcube2™ design software
• 63 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections
• Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires additional sockets, not supplied)


图2. iCEblink40-LP1K评估板外形图和主要硬件特性

图3. iCEblink40-LP1K评估板外形尺寸图


图4. iCEblink40-LP1K评估板电路图
iCEblink40-LP1K评估板主要元件清单:


详情请见:
http://www.latticesemi.com/~/media/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf#search=%22iCE40LP1K%22
和http://www.latticesemi.com/~/media/Documents/UserManuals/EI/iCEblink40LP1KEvaluationKitUsersGuide.PDF

iCE40LPHXFamilyDataSheet.pdf